II. Hardware
1. The basic design of AMIGA computers
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The AMIGA-Hardware as a whole with a detailed description of the cooperation of CPU and Customchips is subject of patent US 4,777,621, titled "Video Game and Personal Computer" published on Oct. 11th 1988. As inventors Commodore-Amiga, Inc. designates: Jay Miner, Joseph C. Decuir and Ronald H. Nicholson. |
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"What Makes It So Great?"
This question was posted by author Sheldon Leemon to the readers of the "Creative Computing"
magazine on page 34 of Sept. 1985 issue. This happened only a few days after the AMIGA was
presented to the public. |
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One of the first publications in German computer mags dealing with the pal version of Amiga,
introduced in summer 1986 is the article called
"Der Amiga mit Maus und Joystick"
by Rolf- Dieter Klein (MC 10/1986, page 100- 102). His result: The most important is however, that
the Amiga is designed as an open system, also access is given to the internal OS kernel,
resect, respect... |
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In this chapter and the following ones we try to give an answer to this question by discussing the published patents and drawings.
Fig. 1 through 3 of patent US 4,777,621 show prior art computer circuitry, which were to be improved by a concept represented in Fig.4. The basic aim is to provide complex video presentations on a television receiver using less circuitry than the prior art devices, and to provide faster processing circuitry more cheaply. The basic operation is explained with reference to Fig. 4 and 5. Note that the custom chips are still not designated. For the following description we refer to Fig.8 of US-Patent 4 874 164 (DENISE and AGNUS) instead.
Herein the system block diagramm shows the system data bus (404) connecting (chip-)RAM (401) to AGNUS (410), DENISE (420) and PAULA (430) directly and to the CPU Motorola 68000 via bidirectional tri-state buffer. The system data bus (404) is bidirectional and is 16 bit.
The register adress bus (405) is bidirectional only with respect to AGNUS chip. The addresses to (chip-)RAM are input from either the CPU (402) or from the AGNUS chip (410) through the (chip-) RAM address bus with selection of either source under the control of multiplexer (407). The register address bus (405), is driven when no DMA is occurring by the low address bits on output lines (408) of the CPU through tristate buffer (409). This allows the microprocessor (402) to read or write the custom chips as if they were random access memory. When a DMA cycle is needed, the AGNUS chip (410) informs CPU (402) by asserting the data bus request line (411). The bus control logic suspends operation of the CPU (402) and switches both tristate buffers (403) and (409) so that CPU (402) no longer has access neither to the system data bus (404) nor register address bus (405). When in this DMA mode AGNUS chip (410) addresses (chip-)RAM (401) with its own (chip-)RAM address bus (406) which is selected by the multiplexer (407) for input to (chip-)RAM (401) under the control of bus logic (412), while simultaneously placing the destination address for the data on the register address bus (405). The register address on the register address bus (405) selects one of a plurality of registers on any of the three custom chips, as the destination of the data from (chip-)RAM (401).
Compared to other state of the art computer designs the performance of AMIGA is enhanced by cycling (chip-)RAM (401) twice as much as the CPU 68000 utilizing the fact that RAM can be cycled much faster, at least during those days when the invention appeared. Thatīs why the CPU uses only every even numbered memory access cycle. The odd cycles are allocated as follows: four cycles for RAM refresh, three cycles for disk DMA, four cycles for audio DMA (two words per channel), 16 cycles for sprite DMA (two words per channel) and 80 cycles for bitplane DMA. By allocating every second memory access cycle (even numbered) the CPU has access to (chip-)RAM at full speed. (chip-)RAM accesses not utilized by the CPU can be allocated to other tasks. Disk DMA, audio DMA, bitplane DMA and sprite DMA have the highest priority during (chip-)RAM access, because missing DMA cycles lead to audible and visible errors in sound and image reproduction. The priority of even numbered memory access cycles is as follows in descending order: Copper DMA, Blitter DMA and CPU. The higher priority of Blitter relative to CPU enables blitter to handle certain tasks much faster than CPU. Therefore there are two independent memory areaes in (chip-)RAM wherein DMA processes can take place at the same time so to speak. As a consequence of the above discussion the CPU will be blocked when Copper and Blitter utilize (chip-)RAM intensively.
(Thomas Unger)